Method for forming polycide gate electrode of metal oxide semiconductor field effect transistor

ABSTRACT

The present invention provides a method for fabricating an improved gate electrode of a MOSFET device. And the method for fabricating a MOSFET device having a polycide gate to which a titanium silicide is applied comprises the steps of sequentially forming a polysilicon layer on a gate insulating layer and a titanium layer in this order, forming a capping layer on the titanium layer and forming a titanium silicide layer by performing a rapid thermal process in nitrogen atmosphere.

FIELD OF THE INVENTION

[0001] The present invention relates to a method for fabricating a semiconductor and, more particularly, to a method for fabricating a metal oxide semiconductor field effect transistor (MOSFET) having a polycide gate electrode.

DESCRIPTION OF THE PRIOR ART

[0002] In the prior art, a polycide, which is stacked with a polysilicon or a tungsten-silicide/polysilicon, has been used as a gate electrode of metal oxide semiconductor field effect transistor (MOSFET). However, as the density of semiconductor devices increases, a line width of gate electrode becomes narrower. So conventional electrode materials may not satisfy a requirement of low resistance that high-integrated devices demand. Accordingly, silicide-type materials such as TiSi₂, CoSi₂, VSi₂, ZrSi₂, NbSi₂, MoSi₂ and HfSi₂ have been developed as a substitution for single polysilicon materials. Through the developments, titanium silicide (TiSi₂) relatively well satisfies requirements for the gate electrode such as a low resistivity, a high melting point, an easiness of forming a thin layer and a line pattern, a thermal stability and so on. So, the titanium silicide (TiSi₂) is considered to be remarkable.

[0003]FIGS. 1A to 1F are cross-sectional views illustrating a conventional MOSFET to which a titanium silicide is applied.

[0004] First, a gate oxide layer 2 is grown on a substrate 1 and a polysilicon layer 3 having a low resistivity is deposited on the gate oxide layer 2 by using the LPCVD (low-pressure chemical vapor deposition) method, and then a titanium layer 4 is deposited on the polysilicon layer 3, as shown in FIG. 1A.

[0005] Next, by performing a RTP (rapid thermal process) for a few seconds with conditions of a nitrogen atmosphere and a specific temperature, a titanium silicide layer 5 having a low resistivity is formed by a reaction between the titanium layer 4 and the polysilicon layer 3, as shown in FIG. 1B.

[0006] A mask oxide layer 6 is deposited on the titanium silicide layer 5, so that the titanium silicide layer 5 may be protected when sidewall spacers are formed by a following dry-etching process, as shown in FIG. 1C.

[0007] Subsequently, a gate electrode is patterned by performing a mask and etching process, as shown in FIG. 1D.

[0008] A screen oxide layer 7 is grown on the exposed substrate 1 by a thermal process, so that it may protect a damage to the substrate 1 when a source/drain region is formed by ion implantation, as shown in FIG. 1E.

[0009] Finally, the lightly doped source/drain region 8 is formed by a low-density ion implantation, as shown in FIG. 1F. Next, after forming sidewall spacers on the sidewall of gate, a heavily doped drain/source region is formed by a high-density ion implantation, leading to a LDD (lightly doped drain) structure.

[0010]FIGS. 2A to 2C are cross-sectional views showing problems caused by the prior art. Referring to FIG. 2A, a titanium nitride layer 9, which is undesirable, is formed between a titanium silicide layer 5 and a mask oxide layer 6. The reason for the formation of the titanium nitride layer 9 is that it is in nitrogen atmosphere that the RTP (rapid thermal process) above described in FIG. 1B is performed. That is, the titanium nitride layer 9 is easily formed since titanium easily reacts with nitrogen. FIG. 2B shows another problem caused by the formation of the titanium nitride layer 9 above described in FIG. 2A. That is, when the screen oxide layer 7 is grown, sidewalls of the gate electrode, which include a polysilicon/titanium-silicide, as well as the substrate 1 are simultaneously oxidized, thereby forming an abnormal oxide layer. At this time, since the titanium nitride is very easily oxidized, the relatively thick oxide layer 10, which is abnormally grown, is formed on the side of the titanium nitride layer 9. In particular, the LDD (lightly doped drain) region may be abnormally formed since the oxide layer 10 abnormally grown acts as a barrier in performing the ion implantation, as shown in FIG. 2C.

SUMMARY OF THE INVENTION

[0011] It is, therefore, an object of the present invention to provide a method for fabricating an improved gate electrode of a MOSFET device.

[0012] In accordance with an aspect of the present invention, there is provided a method for fabricating a MOSFET device having a polycide gate to which a titanium silicide is applied, comprising the steps of sequentially forming a polysilicon layer on a gate insulating layer and a titanium layer in this order, forming a capping layer on the titanium layer and forming a titanium silicide layer by performing a rapid thermal process in nitrogen environment

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other objects and features of the present invention will become apparent from the following description of the preferred embodiments given in connection with the accompanying drawings, in which:

[0014]FIGS. 1A to 1F are cross-sectional views illustrating a conventional MOSFET device;

[0015]FIGS. 2A to 2C are cross-sectional views showing a problem according to the prior art;

[0016]FIGS. 3A to 3E are cross-sectional views illustrating a MOSFET device according to an embodiment of the present invention;

[0017]FIGS. 4A to 4B are cross-sectional views illustrating a MOSFET device according to another embodiment of the present invention; and

[0018]FIGS. 5A to 5C are cross-sectional views illustrating a MOSFET device according to a further another embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] Hereinafter, the present invention will be described in detail referring to the accompanying drawings.

[0020] A method for fabricating an improved gate electrode of a MOSFET device comprises the steps of sequentially forming a polysilicon layer and a titanium layer on a gate insulating layer, forming a capping layer on the titanium layer in order to prevent a titanium nitride layer from being formed on a titanium silicide layer during a rapid thermal process and performing a rapid thermal process in nitrogen atmosphere to form the titanium silicide layer.

[0021]FIGS. 3A to 3B are cross-sectional views illustrating a MOSFET device according to an embodiment of the present invention. As shown in FIG. 3A, after growing a gate oxide layer 2 on a substrate 1, a polysilicon layer 3 having a low resistivity is deposited to a thickness of 1000˜2000 Å by a low-pressure chemical vapor deposition (LPCVD). A titanium layer 4 is then deposited to a thickness of 200˜1000 Å on the polysilicon layer 3. Then, an oxide layer 11 is deposited to a thickness of 500˜1500 Å to cap a surface of the exposed titanium layer 4. The capping of the titanium layer 4 prevents a titanium nitride layer from being formed on the titanium silicide layer during a subsequent rapid thermal process (RTP).

[0022] Next, by performing a rapid thermal process (RTP) in nitrogen atmosphere, the titanium silicide layer 5 is formed by a reaction between the titanium layer 4 and the polysilicon layer 3, as shown in FIG. 3B. At this time, even if the rapid thermal process (RTP) is performed in nitrogen atmosphere, the titanium nitride layer, which is undesirable, is not formed because the oxide layer 11 is capping the surface of the titanium layer 4. When sidewall spacers are formed in subsequent process, the oxide layer 11 may also be used as a mask oxide layer protecting the gate electrode. Meanwhile, the rapid thermal process (RTP) can be performed at a temperature of 800˜850° C. for 10˜30 seconds. In addition, it is possible to perform the rapid thermal process (RTP) in two separate steps in order to effectively form C54 phase having a very low resistivity. The first rapid thermal process (RTP) is performed at a temperature of 700˜750° C. for 10˜30 seconds and the second rapid thermal process (RTP) is performed at a temperature of 750˜850° C. for 10˜30 seconds.

[0023] Subsequently, by performing a mask and etching process, the gate electrode is patterned as shown in FIG. 3C.

[0024] And then, a screen oxide layer 7 is grown on the exposed substrate 1 by a thermal process, as shown in FIG. 3D. Here, since a titanium nitride layer does not exist, the screen oxide layer 7 is in uniformity on the sidewalls of the polycide gate. At this time, the screen oxide layer 7 is formed to a thickness of 30˜100 Å at a temperature of 700˜850° C. If the temperature becomes more than 850° C., an agglomeration may occur on the titanium silicide layer 5 and its resistivity may suddenly increase.

[0025] Finally, a source/drain region 8 having a LDD (lightly doped drain) structure are formed by performing a low-density ion implantation, as shown in FIG. 3E. Here, since an abnormal oxide layer (10 in FIG. 2C) is not formed on the sidewalls of the polycide gate compared to the prior art, the low-density ion implantation is not interrupted so that the LDD (lightly doped drain) structure can normally be formed.

[0026]FIGS. 4A to 4B are cross-sectional views illustrating a MOSFET device according to an another embodiment of the present invention. As shown in FIG. 4A, after growing a gate oxide layer 2 on a substrate 1, a polysilicon layer 3 having a low resistivity is deposited to a thickness of 1000˜2000 Å by a low-pressure chemical vapor deposition (LPCVD). A titanium layer 4 is then deposited to a thickness of 200˜1000 Å on the polysilicon layer 3. And then, a ploysilicon layer or an amorphous layer 12 is deposited to a thickness of 100˜500 Å to cap a surface of the exposed titanium layer 4 and then an oxide layer 11 is again deposited. The capping of the titanium layer 4 prevents a titanium nitride layer from being formed on the titanium silicide layer during a following rapid thermal process (RTP).

[0027] Next, by performing a rapid thermal process (RTP) in nitrogen atmosphere, the titanium silicide layer 5 is formed by a reaction between the titanium layer 4 and the polysilicon layer 3, as shown in FIG. 4B. At this time, even if the rapid thermal process (RTP) is performed in nitrogen atmosphere, the titanium nitride layer, which is undesirable, is not formed because the oxide layer 11 is capping the surface of the titanium layer 4. When sidewall spacers are formed in subsequent process, the oxide layer 11 may also be used as a mask oxide layer protecting the gate electrode. Meanwhile, the rapid thermal process (RTP) can be performed at a temperature of 800˜850° C. for 10˜30 seconds. In addition, it is possible to perform the rapid thermal process (RTP) in two separate steps in order to effectively form C54 phase having a very low resistivity. The first rapid thermal process (RTP) is performed at a temperature of 700˜750° C. for 10˜30 seconds and the second rapid thermal process (RTP) is performed at a temperature of 750˜850° C. for 10˜30 seconds. The processing steps above described in FIGS. 3C to 3E can be applied to a subsequent process.

[0028]FIGS. 5A to 3C are cross-sectional views illustrating a MOSFET device according to a further another embodiment of the present invention.

[0029] As shown in FIG. 5A, after growing a gate oxide layer 2 on a substrate 1, a polysilicon layer 3 having a low resistivity is deposited to a thickness of 1000˜2000 Å by a low-pressure chemical vapor deposition (LPCVD). A titanium layer 4 is then deposited to a thickness of 200˜1000 Å on the polysilicon layer 3. Then, a ploysilicon layer or an amorphous layer 12 is deposited to a thickness of 100˜500 Å to cap a surface of the exposed titanium layer 4. The capping of the titanium layer 4 prevents a titanium nitride layer from being formed on the titanium silicide layer during a following rapid thermal process (RTP).

[0030] Next, by performing a rapid thermal process (RTP) in nitrogen atmosphere, the titanium silicide layer 5 is formed by a reaction between the titanium layer 4 and the polysilicon layer 3, as shown in FIG. 5B. At this time, even if the rapid thermal process (RTP) is performed in nitrogen atmosphere, the titanium nitride layer, which is undesirable, is not formed because the oxide layer 12 is capping the surface of the titanium layer 4. In the same manner, the rapid thermal process (RTP) can be performed at a temperature of 800˜850° C. for 10˜30 seconds. In addition, it is possible to perform the rapid thermal process (RTP) in two separate steps in order to effectively form C54 phase having a very low resistivity. The first rapid thermal process (RTP) is performed at a temperature of 700˜750° C. for 10˜30 seconds and the second rapid thermal process (RTP) is performed at a temperature of 750˜850° C. for 10˜30 seconds.

[0031] Subsequently, as shown in FIG. 5C, a mask oxide layer 7 is deposited in order to protect the gate, i.e., the titanium silicide layer 5 when sidewall spacers are formed in subsequent process.

[0032] In the same manner of the prior art, a gate electrode is patterned by performing a mask and etching process, and then a screen oxide layer is grown. A source/drain region 8 having a LDD (lightly doped drain) structure is formed by performing a low-density ion implantation.

[0033] As a result, by preventing an abnormal growth of an oxide layer on sidewalls of polycide gate to which a titanium silicide is applied, a MOSFET device according to the present invention may have good characteristics of semiconductor device and improve the yield.

[0034] While the present invention has been described with respect to certain preferred embodiments only, other modifications and variation may be made without departing from the spirit and scope of the present invention as set forth in the following claims. 

What is claimed is:
 1. A method for fabricating a MOSFET device having a polycide gate to which a titanium silicide is applied, comprising the steps of: a) sequentially forming a polysilicon layer on a gate insulating layer and a titanium layer in this order; b) forming a capping layer on the titanium layer; and c) forming a titanium silicide layer by performing a rapid thermal process in nitrogen atmosphere.
 2. The method as recited in claim 1, wherein the capping layer is a polysilicon layer.
 3. The method as, recited in claim 1, wherein the capping layer is an amorphous silicon layer.
 4. The method as recited in claim 1, wherein the capping layer is an oxide layer.
 5. The method as recited in claim 1, further comprising the steps of: a) forming a mask insulating layer on the titanium silicide layer; b) patterning the mask insulating layer, the titanium silicide layer and the gate insulating layer by a gate mask and etching process; and c) forming a screen insulating layer on the exposed substrate.
 6. The method as recited in claim 1, wherein the rapid thermal process is performed at a temperature of 800˜850° C. for 10˜30 seconds.
 7. The method as recited in claim 1, wherein the rapid thermal process is performed in separate two steps, wherein the first rapid thermal process is performed at a temperature of 700˜750° C. for 10˜30 seconds and the second rapid thermal process is performed at a temperature of 750˜850° C. for 10˜30 seconds.
 8. The method as recited in claim 5, wherein the screen insulating layer is grown to a thickness of 30˜100 Å at a temperature of 700˜850° C. 